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MULTI-ISSUE 64-BIT MICROPROCESSOR
79RC5000
x
x
Dual issue super-scalar execution core - 250 MHz frequency - Dual issue floating-point ALU operations with other instruction classes - Traditional 5-stage pipeline, minimizes load and branch latencies x Single-cycle repeat rate for most floating point ALU operations x High level of performance for a variety of applications - High-performance 64-bit integer unit achieves 330 dhrystone MIPS (dhrystone 2.1) - Ultra high-performance floating-point accelerator, directly implementing single- and double-precision operations achieves 500mflops - Extremely large on-chip primary cache - On-chip secondary cache controller x MIPS-IV 64-bit ISA for improved computation - Compound floating-point operations for 3D graphics and floating-point DSP - Conditional move operations x Large on-chip TLB x Active power management, including use of WAIT operation
Large, efficient on-chip caches - 32KB Instruction Cache, 32KB Data Cache - 2-set associative in each cach - Virtually indexed and physically tagged to minimize cache flushes - Write-back and write-through selectable on a per page basis - Critical word first cache miss processing - Supports back-to-back loads and stores in any combination at full pipeline rate x High-performance memory system - Large primary caches integrated on-chip - Secondary cache control interface on-chip - High-frequency 64-bit bus interface runs up to 125MHz - Aggregate bandwidth of on-chip caches, system interface of 5.6GB/s - High-performance write protocols for graphics and data communications x Compatible with a variety of operating systems - WindowsTM CE - Numerous MIPS-compatible real-time operating systems x Uses input system clock, with processor pipeline clock multiplied by a factor of 2-8 x Industrial and commercial temperature range
Unpacker/Packer
Floating-point Control
The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
PDUJDL' NFRO% PDUJDL' NFRO% PDUJDL' NFRO% PDUJDL' NFRO%
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Phase Lock Loop Data Set A Store B uffer SysAD W rite Buffer Read Buffer Data Set B DB us Control Tag Floating Point Register File Joint T LB Coprocessor 0 System /M emory Control DVA Integer Control AuxTag L oad Aligner Integer Register File Integer/Address Adder Data T LB Virtual Shifter/Store Aligner Logic Unit AB us Integer M ultiply, Divide FPIB us Address B uffer Instruction Tag A ITL B Physical Instruction Tag B Instruction Set B IntIB us Data Tag A DT LB Physical Instruction Select Integer Instruction Register FP Instruction Register Instruction Set A
Floating Point M Add,Add,Sub, Cvt Div, SqRt
IVA PC Increm enter B ranch Adder Instruction TL B Virtual Program Counter
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2001 Integrated Device Technology, Inc.
April 10, 2001
DSC 5719
79RC5000
The RC5000 serves many performance critical embedded applications, such as high-end internetworking systems, color printers, and graphics terminals. The RC5000 is optimized for high-performance applications, with special emphasis on system bandwidth and floating point operations, through integration of high-performance computational units and a highperformance memory hierarchy. For this class of application, the result is a relatively low-cost CPU capable of approximately 330 Dhrystone MIPS. IDT's objectives in offering the RC5000 include: x Offering a high performance upgrade path to existing embedded customers in the internetworking, office automation and visualization markets. x Providing a significant improvement in the floating- point performance currently available in a moderately priced MIPS CPU. x Providing improvements in the memory hierarchy of desktop systems by using large primary caches and integrating a secondary cache controller. x Enabling improvements in performance through the use of the MIPS-IV ISA.
The RC5000 implements the MIPS-IV 64-bit ISA, including CP1 and CP1X functional units (and their instruction set).
H QLO H SL3 U H J HW Q,
Load Store
2 2 8
1 1 8
MULT/MULTU DMULT/DMULTU DIV/DIVU DDIV/DDIVU Other Integer ALU Branch Jump
12 36 68 1 2 2
12 36 68 1 2 2
Table 1 Integer Instruction Execution Speed
The RC5000 recognizes two general classes of instructions for multiissue: x Floating-point ALU x All others These instruction classes are pre-decoded by the RC5000, as they are brought on-chip. The pre-decoded information is stored in the instruction cache. Assuming that there are no pending resource conflicts, the RC5000 can issue one instruction per class per pipeline clock cycle. Note that this broad separation of classes insures that there are no data dependencies to restrict multi-issue. However, long-latency resources in either the floating-point ALU (e.g. DIV or SQRT instructions) or instructions in the integer unit (such as multiply) can restrict the issue of instructions. Note that the R5000 does not perform out-of-order or speculative execution; instead, the pipeline slips until the required resource becomes available. There are no alignment restrictions on dual-issue instruction pairs. The RC5000 fetches two instructions from the cache per cycle. Thus, for optimal performance, compilers should attempt to align branch targets to allow dual-issue on the first target cycle, since the instruction cache only performs aligned fetches.
The RC5000's short pipeline keeps the load and branch latencies very low. The caches contain special logic that allows any combination of loads and stores to execute in back-to-back cycles without requiring pipeline slips or stalls. (This assumes that the operation does not miss in the cache.)
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The RC5000 is a limited dual-issue machine that utilizes a traditional 5-stage integer pipeline. This basic integer pipeline of the RC5000 is illustrated in Figure 1. The integer instruction execution speed is tabulated (in number of pipeline clocks) as follows:
April 10, 2001
79RC5000
I0 1I 2I 1R 2R 1A 2A 1D 2D 1W 2W
I1
1I
2I
1R
2R
1A
2A
1D
2D
1W
2W
I2
1I
2I
1R
2R
1A
2A
1D
2D W
1
I3
1I
2I
1R
2R
1A
2A
1D
I4
1I
2I
1R
2R
1A
one cycle
Figure 1 R5000 Integer Pipeline Stages
Key to Figure 1I-1R 2I 2A-2D 1D 1D-2D 2R 2R 2R 2R 1A 1A-2A 1A 2A 1A 2W Instruction cache access Instruction virtual to physical address translation Data cache access and load align Data virtual to physical address translation Virtual to physical address translation Register file read Bypass calculation Instruction decode Branch address calculation Issue or slip decision Integer add, logical, shift Data virtual address calculation Store align Branch decision Register file write
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April 10, 2001
79RC5000
The RC5000 contains the following computational units:
where P is the maximum power consumption at hot temperature, calculated by using the maximum ICC specification for the device. Typical values for CA at various airflows are shown in Table 1. CA
Airflow (ft/min) PGA BGA 0 16 14 200 7 6 400 5 4 600 3 3 800 2.5 2.5 1000 2 2
Integer ALU. The RC5000 implements a full, single-cycle 64-bit ALU for all integer ALU functions other than multiply and divide. Bypassing is used to support back-to-back ALU operations at the full pipeline rate, without requiring stalls for data dependencies. Integer Multiply/Divide Unit. This unit is separated from the primary ALU, to allow these longer latency operations to run in parallel with other operations. The pipeline stalls only if an attempt to access the HI or LO registers is made before the operation completes. Floating-point ALU. This unit is responsible for all CP1/CP1X ALU operations other than DIV/SQRT. The unit is pipelined to allow a singlecycle repeat rate for single-precision operations Floating-point DIV/SQRT unit. This unit is separated from the other floating-point ALU, so that these long latency operations do not prevent the issue of other floating point operations. In addition, the RC5000 implements separate logical units to implement loads, stores, and branches.
Per the RC5000 Documentation errata, Revision 1.0, dated February 1999 and per the RC5000 Device errata, dated February 1999, mode bits 20, 33 and 37 must be set to 1.
The input clock operates in a frequency range of 33MHz to 100MHz. The pipeline frequency for the RC5000 is 2 to 8 times the input clock (up to the maximum for the speed grade of CPU).
January 1996: Corrected pin list for Clock/Control, Initialization, and Secondary Cache interfaces in Pin Description section. Changed pins AA19 and AA21 from Vcc to Vss in Advance Pin-Out section. March 1997: Upgraded data sheet status from "Preliminary" to Final. Added section on thermal considerations. Added section on absolute maximum ratings. June 1997: Revised Power Consumption and System Interface Parameters. September 1997: Added user notation on Boot Mode Bits 20 and 33 for 200 MHz frequency. June 1998: Added 250 MHz. Changed naming conventions. June 1999: Added 267 MHz and 300 MHz. October 28, 1999: Added industrial temperature data and revised package designation code in the Ordering Information section. March 23, 2000: Expanded the data presentation in the System Interface Parameters table and revised the values in this table. April 10, 2001: In the Data Output and Data Output Hold categories of the System Interface Parameters table, changed values in the Min column for all speeds from 1.5 and 1.0 to 0.
The RC5000 utilizes special packaging techniques, to improve the thermal properties of high-speed processors. The RC5000 is packaged using cavity down packaging in a 223-pin PGA package with integral thermal slug, and a 272-pin BGA package. These packages effectively dissipate the power of the CPU, increasing device reliability. The RC5000 utilizes an all-aluminum package with the die attached to a normal copper lead frame mounted to the aluminum casing. Due to the heat-spreading effect of the aluminum, the package allows for an efficient thermal transfer between the die and the case. The aluminum offers less internal resistance from one end of the package to the other, reducing the temperature gradient across the package and therefore presenting a greater area for convection and conduction to the PCB for a given temperature. Even nominal amounts of airflow will dramatically reduce the junction temperature of the die, resulting in cooler operation. The RC5000 is guaranteed in a case temperature range of 0 to +85 C. The type of package, speed (power) of the device, and airflow conditions affect the equivalent ambient temperature conditions that will meet this specification. The equivalent allowable ambient temperature, TA, can be calculated using the thermal resistance from case to ambient (CA) of the given package. The following equation relates ambient and case temperatures: TA = TC - P * CA
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HWR1 HWR1 HWR1 HWR1
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Table 2 Thermal Resistance (yCA) at Various Airflows
Note: The RC5000 implements advanced power management to substantially reduce the average power dissipation of the device. This operation is described in the IDT79RV5000 RISC Microprocessor Reference Manual.
April 10, 2001
79RC5000
SysCmdP System Interface ValidIn* ValidOut* ExtRqst* Release* RdRdy* WrRdy*
16
ScTOE* ScCLR* ScDCE* ScDOE* ScCWE* ScLine (15:0) ScMATCH ScVALID
Int (5:0)* NMI*
Clock Interface
VccP VssP Vcc Vss
34 34
BigEndian ModeClock VccOk ColdReset* Reset* Initialization Interface JTAG Interface ModeIN
JTDI JTDO JTMS JTCK
Figure 2 RC5000 Logic Symbol Diagram
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Interrupt Interface
SysClock
RC5000 Logic Symbol
6
Secondary Cache Interface
PDUJDL' FLJR/ PDUJDL' FLJR/ PDUJDL' FLJR/ PDUJDL' FLJR/
SysAD(63:0) SysADC(7:0) SysCmd(8:0)
64 8 9 2
ScWord (1:0) ScTCE* ScTDE*
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79RC5000
System interface ExtRqst* Release* RdRdy* WrRdy* ValidIn* Input Output Input Input Input External Request. Signals that the system interface needs to submit an external request. Release Interface. Signals that the processor is releasing the system interface to slave state Read Ready. Signals that an external agent can now accept a processor read. Write Ready. Signals that an external agent can now accept a processor write request. Valid Input. Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. Valid Output. Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. System Address/Data bus. A 64-bit address and data bus for communication between the processor and an external agent. System Address/Data check bus. An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles. System Command/data identifier bus. A 9-bit bus for command and data identifier transmission between the processor and an external agent. Reserved System Command/data identifier bus parity. For the RC5000, unused on input and zero on output.
ValidOut*
Output
SysAD(63:0) SysADC(7:0) SysCmd(8:0) SysCmdP
Input/ Output Input/ Output Input/ Output Input/ Output
Clock/control interface SysClock VCCP VSSP Input Input Input Master Clock. Master clock input at the bus frequency. The pipeline clock is derived by multiplying this clock up. Quiet VCC for PLL. Quiet VCC for the internal phase locked loop. Quiet VSS for PLL. Quiet VSS for the internal phase locked loop.
Interrupt interface Int(5:0)* NMI* JTAG interface: JTDI JTCK Input Input JTAG Data In. Connected directly to JTDO. No JTAG implemented; should be pulled High. JTAG Clock Input. Unused input; should be pulled High. Table 3: RC5000 Signal Names and Descriptions (Page 1 of 2) Input Input Interrupt. Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register. Non-maskable interrupt. Non-maskable interrupt, ORed with bit 6 of the interrupt register.
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April 10, 2001
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The RC5000 implements a bus similar to that of the RC4700. Table 2 lists and describes the RC5000 signals.
79RC5000
JTDO JTMS
Output Input
JTAG Data Out. Connected directly to JTDI. If no external scan used, this is a no connect. JTAG Command. Unused input. Should be pulled High.
Initialization interface: VCCOk Input VCC is OK. When asserted, this signal indicates to the RC5000 that the power supply has been above Vcc minimum for more than 100 milliseconds and will remain stable. The assertion of VCCOk initiates the reading of the boot-time mode control serial stream. Cold Reset. This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with SysClock. Reset. This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously for a cold reset, or syn chronously to initiate a warm reset. Reset must be synchronously de-asserted with SysClock. Boot Mode Clock. Serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six. Boot Mode Data In. Serial boot-mode data input. Endian mode select. Allows the system to change the processor addressing mode without rewriting the mode ROM. If endianness is to be specified by using the BigEndian pin, program mode ROM bit 8 to 0; if endianness is to be specified by the mode ROM, ground the BigEndian pin.
ColdReset* Reset*
Input Input
ModeClock ModeIn BigEndian
Output Input Input
Secondary cache interface: ScCLR* ScCWE*(1:0) ScDCE*(1:0) ScDOE* ScLine (15:0) ScMATCH ScTCE* ScTDE* ScTOE* ScWord (1:0) ScValid Output Output Output Input Output Input Output Output Output Input/ Output Input/ Output Secondary Cache Block Clear. Clears all valid bits in those Tag RAM's which support this function. Secondary Cache Write Enable. Asserted during writes to the secondary cache Data RAM Chip Enable. Chip Enable for Secondary Cache Data RAM Data RAM Output Enable. Asserted by the external agent to enable data onto the SysAD bus Data RAM Output Enable. Cache line index for secondary cache Secondary cache Tag Match. Asserted by Tag RAM on Secondary cache tag match Secondary cache Tag RAM Chip Enable. Chip enable for secondary cache tag RAM. Secondary cache Tag RAM Data Enable. Data Enable for Secondary Cache Tag RAM. Secondary cache Tag RAM Output Enable. Tag RAM Output enable for Secondary Cache Tag RAM's Secondary cache Word Index. Determines correct double-word of Secondary cache Index Secondary cache Valid. Always driven by the CPU except during a cache probe operation, when it is driven by the tag RAM. Table 3: RC5000 Signal Names and Descriptions (Page 2 of 2)
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April 10, 2001
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79RC5000
VTERM TC TBIAS TSTG IIN IOUT
1. 2. 3. 4. 5.
Terminal Voltage with respect to GND Operating Temperature (case) Case Temperature Under Bias Storage Temperature DC Input Current DC Output Current
-0.51 to +4.6 0 to +85 -55 to +125 -55 to +125 202 504
-0.51 to +4.6 -40 to +85 -55 to +125 -55 to +125 203 505
V C C C mA mA
IN minimum = -2.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5 Volts. .When VIN < 0V or VIN > VCC. .When VIN < 0V or VIN > VCC. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
Commercial Industrial
0C to +85C (Case) -40C to +85C (Case)
0V 0V
3.3V5%
3.3V5%
(VCC= 3.3V 5%; Tcase = 0C to +85C for commercial or Tcase = -40C to +85C for industrial)
Note: Boot Mode Bits 20, 33 and 37 must be set to "1" for all frequencies
Min 100 3 3 33 11.1 -- -- --
Max 180 -- -- 90 30 2.5 2.5 256 tSCP
Min 100 3 3 33 10 -- -- --
Max 200 -- -- 100 30 2 2 256 tSCP
Min 100 3 3 33 8 -- -- --
Max 250 -- -- 125 30 2 2 256 tSCP
Pipeline Clock Frequency SysClock HIGH SysClock LOW SysClock Frequency SysClock Period SysClock Rise Time1 SysClock Fall Time1 ModeClock Period
1.
PCLk tSCHIGH tSCLOW
--
ns ns MHz ns ns ns ns
tSCP tSCRise tSCFall tModeCKP
Rise and Fall times are measured between 10% and 90%
8 of 15
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Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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April 10, 2001
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Load Derate CLD -- -- 2 -- 2 -- 2 ns/25pF
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79RC5000
Note: 50 pf loading on external output signals
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Data Input
Data Output
Data Output Hold tDOH1
1.
Mode Data Setup
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Mode Data Hold
Guaranteed by design.
tDS
tDH
tDO = Max tDM = Min
tDH
tDS
mode 14..13 = 01 (slowest)
mode 14..13 = 00 (67%)
mode 14..13 = 11 (83%)
trise = 3ns tfall = 3ns
mode 14..13 = 10 (fastest)
mode 14..13 = 01 (slowest, 50%)
mode 14..13 = 00 (67%)
mode 14..13 = 11 (83%)
mode 14..13 = 10 (fastest, 100%) 01
--
--
Min
0
4
9 of 15 Max -- -- 01 0 0 0 01 01 Min 0.5 1.5 0 Min Min 0 4 Max Max 11 9 8 7 -- -- -- -- -- -- Max -- -- Min 01 01 01 0 0 0 0 0.5 Min 1.5 01 Min 0 4 Max Max -- -- -- -- -- -- -- Max -- 11 9 7 5 Min ns ns 0 0 0 0 0.5 1.5 01 01 01 Min 01 Max -- -- -- -- -- -- 7 6 5 4.7 Max
Master Clock Cycle
Master Clock Cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
April 10, 2001
79RC5000
Min -- VCC - 0.1V -- 2.4V -0.5V 0.7VCC -- -- -- -- --
Max 0.1V -- 0.4V -- 0.2VCC VCC + 0.5V 10uA 10pF 10pF 10pF 20uA
Min -- VCC - 0.1V -- 2.4V -0.5V 0.7VCC -- -- -- -- --
Max 0.1V -- 0.4V -- 0.2VCC VCC + 0.5V 10uA 10pF 10pF 10pF 20uA
Min -- VCC - 0.1V -- 2.4V -0.5V 0.7VCC -- -- -- -- --
Max 0.1V -- 0.4V -- 0.2VCC VCC + 0.5V 10uA 10pF 10pF 10pF 20uA -- --
VOL VOH VOL VOH VIL VIH IIN CIN CIO Cclk I/OLEAK
|IOUT|= 20uA
|IOUT|= 4mA
0 VIN VCC -- --
Input/Output Leakage
Max 180/45MHz 120mA 1100mA
Max 200/50MHz 120mA 1300mA
Max 250/62.5MHz -- 120mA 1800mA
System Condition Icc Standby Active
CL = 50 pF CL = 50pF Pipelined writes or write re-issue Tc = 25oC
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=+0 ]+0
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(Vcc = 3.3V 5%; Tcase = 0C to +85C for commercial or Tcase = -40C to +85C for industrial)
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April 10, 2001
79RC5000
The RC5000 is available in two packages, the 223-pin CPGA and the 272-ball SBGA. The 223-pin CPGA package is shown in Figure 2 and Table 3; information on the SBGA package is shown in Figure 3 and Table 4.
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223-Pin CPGA
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
Figure 3 RC5000 223-pin CPGA Pin Orientation (Bottom View)
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79RC5000
A2 A3 A4 A5 A6 A7 A8 A9
Vcc Vss Vcc Vss Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vss Vcc Vss Vss Vss
C5 C6 C7 C8 C9
SysADC[6] SysAD[16] SysAD[50] SysAD[22] SysAD[24] SysAD[28] SysAD[62] SysAD[44] SysAD[10] SysAD[38] SysAD[4] SysAD[34] SysAD[2] Vss Vss INT3* INT5* Release* Vcc
E18
Vcc Vcc
K17 K18 L1 L2 L3 L4 L15 L16 L17 L18 M1 M2 M3 M4
VssP Vss Vss
R6 R7 R8 R9
SysAD[51]
U9
SysAD[63] SysAD[13] SysAD[11] SysAD[9]
F1 F2 F3 F4 F15 F16 F17 F18 G1 G2 G3 G4 G15 G16 G17 G18 H1 H2 H3 H4 H15 H16 H17 H18 J1 J2 J3 J4 J15 J16 J17 J18 K1 K2 K3 K4S K15 K16
SysAD[55] SysAD[27] SysAD[31] SysAD[43] SysAD[39] SysAD[35] SysAD[1] ScWord[1] ScLine[0] ScLine[3] ScLine[6] Vss Vss SysAD[15] SysAD[47] SysAD[17] SysAD[19] SysAD[23] SysAD[57] SysAD[29] Vcc SysAD[45] SysAD[41] SysAD[7] SysAD[5] SysAD[33] Reset* ScLine[1] Vcc Vcc Vcc Vcc Vss SysAD[21] SysAD[53] SysAD[25] SysAD[59] SysAD[61]
U10 U11 U12 U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18
Reserved ScValid INT[1]* ScDCE[0]* ScCWE[0]* ScTDE* Vss Vss Reserved Reserved Reserved ScCLR* ScTCE* ModeIn Vcc Vcc Reserved Reserved Reserved VccOK ModeClock SysClock Vss Vss WrRdy* ValidIn* ExtReq* JTDO JTDI JTCK Vcc Vcc ScMatch RdRdy* cDOE* JTMS VccP
SysCmd[8] SysCmd[7] SysCmd[5] ScLine[12] ScLine[14] ScLine[15] Vcc Vcc SysCmd[6] SysCmd[4] SysCmd[1] ScLine[8] ScLine[10] ScLine[13] Vss Vss SysCmd[3] SysCmd[2] SysADC[7] ScLine[5] ScLine[7] ScLine[11] Vcc Vcc SysCmd[0] SysCmdP SysADC[1] ScLine[2] ScLine[4] ScLine[9] Vss Vcc SysADC[5] SysADC[3] BigEndian SysAD[49]
R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 U1 U2 U3 U4 U5 U6 U7 U8
SysAD[37] SysAD[3] ScWord[0] Vcc Vss Vss Vss Vss Vcc Vss Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vss Vcc Vss
C10 C11 C12 C13 C14 C15 C16 C17 C18 D1 D2I D3 D4 D5 D6 D7 D8 D9 D10 D11 D12S D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E15 E16 E17
A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6] B7] B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C4
M15 M16 M17 M18 N1 N2 N3 N4 N15 N16 N17 N18 P1 P2 P3 P4 P15 P16 P17 P18 R1 R2 R3 R4 R5
Vss Vcc SysADC[4] SysADC[0] SysAD[18 SysAD[20] SysAD[54] SysAD[26] 0SysAD[58] SysAD[30] SysAD[46] SysAD[12] SysAD[40] SysAD[6] Vss Vcc Vcc Vcc Vcc ValidOut* NMI*
SysADC[2] SysAD[48] SysAD[52] SysAD[56] SysAD[60] SysAD[14] SysAD[42] SysAD[8] SysAD[36] ColdReset* SysAD[0] ScTOE* Vcc Vss INT[0]* INT[2]* NT[4]* SysAD[32] ScDCE[1]* ScCWE[1]*
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April 10, 2001
QRLWFQX)
QL3
QRLWFQX) QL3
QRLWFQX)
QL3
QRLWFQX)
QL3 QRLWFQX)
WXRQL3 $*3& QL3 WXRQL3 $*3& QL3 WXRQL3 $*3& QL3 WXRQL3 $*3& QL3
QL3 QRLWFQX) QL3
79RC5000
HJDNFD3 $*%6 OOD% HJDNFD3 $*%6 OOD% HJDNFD3 $*%6 OOD% HJDNFD3 $*%6 OOD%
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K 272-Ball SBGA L M N P R T U V W Y AA
Figure 4 Ball Grid Array Package (Bottom View) 13 of 15 April 10, 2001
79RC5000
WXRQL3 $*%6 OOD% WXRQL3 $*%6 OOD% WXRQL3 $*%6 OOD% WXRQL3 $*%6 OOD%
Pkg Pin Function AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 B1 B2 B3 B4 Vss Vcc Vss ValidOut* Vss Int*0 Vss Reserved Vss WrRdy* Vss ScMatch Vss SysCmd6 Vss SysCmd2 Vss SysADC3 Vss Vcc Vss Vss Vcc Vss SysAD32 Vss ScCWE*1 Vss VCCOK Vss MasterClk Vss ScLine15 Vss ScLine12 Vss ScLine7 Vss ScLine2 Vss Vcc Vss Vcc Vcc Vcc SysAD2 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 D1 D2 D3 D4 D5 D6 D7 D8 N/C Vcc Vcc Vcc Vss Vcc Vcc Vss Vcc Vcc Vcc Vss Vcc Vss Vcc Vcc
Pkg Pin Function SysAD0 ScTOE* ScCLR* ScTDE* ModeClock JTDI JTCK ScLine14 ScLine10 ScLine9 ScLine6 ScLine3 ScLine1
Pkg Pin D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 E1 E2 E3 E4 E18 E19 E20 E21 F1 F2 F3 F4 F18 F19 F20 F21 G1 G2 G3 G4 G18 G19 G20 G21 H1 H2 H3 H4 H18 H19 H20 H21 J1
Function Vss Vcc Vccp Vcc Vss Vcc Vcc Vss Vcc Vss Vcc Vcc Vcc Vss SysAD36 SysAD4 Vcc Vcc ScWord1 ScWord0 Vss SysAD8 SysAD38 SysAD6 Vss Vss SysAD1 SysAD33 SysAD3 Vss SysAD10 SysAD40 Vcc Vcc SysAD35 SysAD5 Vss SysAD42 SysAD44 SysAD12 Vcc Vcc SysAD7 SysAD39 SysAD37 Vss
Pkg Pin Function J2 J3 J4 J18 J19 J20 J21 K1 K2 K3 K4 K18 K19 K20 K21 L1 L2 L3 L4 L18 L19 L20 L21 M1 M2 M3 M4 M18 M19 M20 M21 N1 N2 N3 N4 N18 N19 N20 N21 P1 P2 P3 P4 P18 P19 P20 SysAD46 SysAD14 Vss Vss SysAD9 SysAD41 Vss SysAD60 SysAD30 SysAD62 Vcc Vcc SysAD11 SysAD43 SysAD13 Vss SysAD58 SysAD28 Vcc Vcc SysAD45 SysAD63 Vss SysAD26 SysAD56 SysAD24 Vcc Vcc SysAD29 SysAd61 SysAD31 Vss SysAD54 SysAD22 Vss Vss SysAD27 SysAD59 Vss SysAD50 SysAD52 SysAD20 Vcc Vcc SysAD25 SysAD57
Pkg Pin P21 R1 R2 R3 R4 R18 R19 R20 R21 T1 T2 T3 T4 T18 T19 T20 T21 U1 U2 U3 U4 U18 U19 U20 U21 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21
Function SysAD55 Vss SysAD18 SysAD48 Vcc Vcc SysAD53 SysAD23 Vss SysAD16 SysADC0 SysADC2 Vss Vss SysAD19 SysAD51 SysAD21 Vss SysADC4 SysADC6 Vcc Vcc SysAD17 SysAD49 Vss Vcc Vcc Vcc Vss NMI* Vss Vcc Vcc Vss Vcc Vcc Vcc Vss Vcc Vcc Vss Vcc Vss Vcc Vcc Vcc
Pkg Pin Function W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Vss Vcc Vcc Vcc Int*5 Int*4 Int*1 Reserved Reserved Reserved ValidIn* ScDOE* SysCmd7 SysCmd4 SysCmd1 SysADC7 SysADC5 SysAD47 BigEndian Vcc Vss Vcc Vcc Vcc Release* Int*3 Int*2 ScValid Reserved Reserved Reserved ExtRqst* RdRdy* SysCmd8 SysCmd5 SysCmd3 SysCmd0 SysCmdP SysADC1 SysAD15 Vcc Vcc
ColdReset* SysAD34 ScDCE*1 ScDCE*0 ScCWE*0 ScTCE* ModeIn JTDO Vssp JTMS ScLine13 ScLine11 ScLine8 ScLine5 ScLine4 ScLine0 Reset*
14 of 15
April 10, 2001
79RC5000
QRLWDP URIQ, JQLUHGU2 QRLWDP URIQ, JQLUHGU2 QRLWDP URIQ, JQLUHGU2 QRLWDP URIQ, JQLUHGU2
IDT79 YY Operating Voltage XXXX Device Type 999 Speed A Package A Temp range/ Process Blank I Commercial Temperature (0C to +85C Case) Industrial Temperature (-40C to +85C Case) G 223-ball CPGA BS272 272-ball SBGA 180 200 250 180 MHz Pipeline 200 MHz Pipeline 250 MHz Pipeline 5000 RV Multi-Issue 64-bit Microprocessor 3.3+/-5%
VQRLWDQLEPR& GLOD9 VQRLWDQLEPR& GLOD9 VQRLWDQLEPR& GLOD9 VQRLWDQLEPR& GLOD9
IDT79RV5000 - 180, 200MHz IDT79RV5000 - 180, 200, 250MHz IDT79RV5000 - 180, 200MHz G BS272 BS272 I CPGA package SBGA package SBGA package
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for Tech Support: email: rischelp@idt.com phone: 408-492-8208
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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April 10, 2001
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